With an SoC (System-on-a-Chip) various types of signal processing are performed by one chip. Accordingly, an SoC includes various IP (Intellectual Property) macros such as high-speed interface I/O (Input/Output) and an ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter). A PLL (Phase Locked Loop) is used as a supplier of an input clock which operates each IP macro. However, clock routing from the PLL to each IP macro is complex, so power consumption increases.
In recent years attention has been riveted on DDC (Deeply Depleted Channel) transistors which operate at low voltage. With DDC transistors, for example, a back bias is controlled by a charge pump circuit. This mikes it possible to operate at low voltage while decreasing a leakage current.
Japanese Laid-open Patent Publication No. 2006-277557
Japanese Laid-open Patent Publication No. 2008-118098
By the way, the restriction of allowable jitter is placed on an input clock to each IP macro. A clock path is placed so as to meet this restriction. However, noise produced at the time of control of a back bias of a DDC transistor included in a clock buffer on the clock path causes an increase in the amount of jitter. As a result, the restriction of allowable jitter may fail to be met.